Generally, computing devices, such as computers, laptops, and servers, include a memory and a processor. The memory and the processor exchange data with the help of a controller. The controller, which is usually implemented in an integrated circuit (IC) chip, facilitates exchange of data in the form of data signals. The data signals are sent through input-output (IO) cells of the IC chip.
The frequency of operation of the memory and that of the IO cells has considerably increased over the years. In addition, the amount of data exchanged per unit time, also called a data rate, has also increased. Traditionally, data signals were exchanged at one edge of a clock cycle, such as in a Single Data Rate (SDR) Synchronous Dynamic Random Access Memory (SDRAM). Nowadays, exchange of data signals at both edges of the clock cycle, such as in a Dual Data Rate (DDR) SDRAM, has also become popular.
With the increasing data rate, the controller and IO cells have also been upgraded. This upgrade is necessary for reliable operation of the IO cells at the increased frequency. Even a small variation in the clock signal or the data signals may cause timing skews or uncertainty in the data signals at the memory input.
Timing skews or uncertainty in the data signals is mainly caused by a jitter in the clock signal or the data signals. A jitter is any variation in the rising or falling edge of a signal from its ideal position. It can be measured as the time difference between the actual rising or falling edge and the corresponding ideal rising or falling edge of the signal. For reliable exchange of data signals, jitter specifications should be within certain limits, as specified by a standardization body called “Joint Electron Device Engineering Council” (JEDEC). For example, for a 400 MHz DDR2 SDRAM data signals, a cycle-to-cycle jitter, a duty cycle jitter, and a period jitter should be within 200 ps, 100 ps, and 100 ps, respectively.
The IO cells thus need to be designed accordingly to keep jitter specifications within desired limits for a given system. The designers of the IO cells have to ensure that the jitter specifications are met. In addition, with the increasing frequency of operation, the time for which data signal is valid is also decreasing. The IO cells, thus, have to be tested to ensure that signals being exchanged through the IO cells are reliably communicated to the memory input.